Exemplary embodiments relate generally to a method of manufacturing a nonvolatile memory device and, more particularly, to a method of manufacturing a nonvolatile memory device, which is capable of reducing the grain size of a control gate.
A nonvolatile memory device includes a number of memory cells for storing data. A NAND flash memory cell is described as an example. The NAND flash memory cell has a stack structure, including a gate insulating layer for electron tunneling, a floating gate for storing data, a dielectric layer for coupling, and a control gate for transferring a driving voltage.
With the gradual increase in the degree of integration of nonvolatile memory devices, sizes of memory cell have been reduced and therefore the gap between neighboring memory cells has been narrowed. In particular, with a reduction in the gap between the memory cells, a process of forming the control gate has gradually become difficult. More particularly, to form the control gate, polysilicon is grown and formed on the dielectric layer. If the grain size of polysilicon is large and uniform, a void can be generated between the grains. The voids generated in the control gate can lead to a difference in the electrical properties between different memory cells when the memory cells are operated. Furthermore, since the voids generated in the control gate can be thermally moved, the coupling ratio of a corresponding memory cell is lowered if the voids adhere to the dielectric layer. If an abnormal cell occurs as described above, the distribution characteristics of the nonvolatile memory device deteriorate.